A motherboard of a computer system is generally provided with a central processing unit (CPU), a chipset and some peripheral circuits. The CPU is the core component of a computer system for processing and controlling operations and cooperation of all the other components in the computer system. The chipset may be in various forms but generally includes a north bridge chip and a south bridge chip, which are used to control communication between the CPU and the peripheral circuits. In general, the north bridge chip serves for the communication with the high-speed buses while the south bridge chip serves for the communication with low-speed devices in the system.
FIG. 1A is a schematic functional block diagram illustrating some devices disposed on or coupled to a motherboard 1 in a single CPU computer system. On the motherboard 1, a chipset 2 including a north bridge chip 20 and a south bridge chip 21 is electrically connected to the CPU 10 via a front side bus (FSB) 22. On the motherboard 1, an accelerated graphics port (AGP) interface 31 and a random access memory (RAM) 32 are electrically connected to the north bridge chip 20 via an AGP bus 311 and a memory bus 321, respectively. A peripheral component interconnect (PCI) interface 30 is electrically connected to the south bridge chip 21 via a PCI bus 301. In addition, an industry standard architecture (ISA) interface 40, an integrated device electronics (IDE) interface 41, a universal serial bus (USB) interface, an external keyboard device 43 and an external mouse device 44, which operate at a low speed, are electrically connected to the south bridge chip 21.
In the above architecture, the standard of the FSB 22 should support both the north bridge chip 20 and the CPU 10 coupled thereto, as illustrated in FIG. 1B. If the transmission standard of the north bridge chip 20 via the FSB 22 mismatched that of the CPU 10, e.g. different in width (bits) or bit speed (MHz), the communication between the north bridge chip 20 and the CPU 10 would fail or some of transmitted data might be lost. For example, a bridge chip adapted to a processor with a 64-bit front-side-bus width will be unsuited to another processor with a 32-bit front-side-bus width. Otherwise, a half of the transmitted data will not be received. In other words, the compatibility between the CPU and the bridge chip is critical to data transmission.
Some possible combinations of front-side-bus width of the CPU and the north bridge chip are exemplified with reference to FIGS. 2A˜2D. The front side bus (FSB) includes an address bus and a data bus respectively for address and data transmission between the CPU and the north bridge chip. In the example of FIG. 2A, the CPU 101 and the north bridge chip 201 have the same FSB width, e.g. both 32 bits for address transmission and both 64 bits for data transmission. Since the transmission standards of the CPU 101 and the north bridge chip 201 are compatible with each other, the system can operate normally. Likewise, in the example of FIG. 2B, the CPU 102 and the north bridge chip 202 have the same FSB width, e.g. both 13 bits for address transmission and both 32 bits for data transmission. Since the transmission standards of the CPU 102 and the north bridge chip 202 are compatible with each other, the system can also operate normally. In the example of FIG. 2C, on the other hand, while the CPU 102 has 13-bit width for address transmission and 32-bit width for data transmission, the north bridge chip 201 has 32-bit width for address transmission and 64-bit width for data transmission. Since the transmission standards of the CPU 102 and the north bridge chip 201 are not consistent, the communication between the CPU 102 and the north bridge chip 201 cannot be normally performed. A similar idle situation is illustrated in FIG. 2D, where the CPU 101 allowing 32-bit width for address transmission and 64-bit width for data transmission is inconsistent with the north bridge chip 201 allowing 13-bit width for address transmission and 32-bit width for data transmission. In addition to FSB width, incompatible transmission speeds between the CPU and bridge chip will also adversely affect the operation of the computer system.
With increasing tendency to compactness of devices, portable electronic apparatus such as personal digital assistants (PDAs) or notebook computers require smaller motherboards or chips with lower pin numbers compared to a desktop computer that needs to support various applications. Accordingly, CPUs with different transmission standards for optional requirement of performance or compactness and bridge chips with different transmission standards for conforming to the transmission standards of the corresponding CPUs need be manufactured and stocked for selection to avoid the mismatching problems.